Template:Infobox CPU architecture/doc

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This template is for CPU instruction set architectures.

Usage

<syntaxhighlight lang="wikitext"> </syntaxhighlight>

Description

<syntaxhighlight lang="wikitext">

Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
DesignerDesigner of the architecture
BitsWidth of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
IntroducedYear introduced
VersionVersion/revision of architecture/ISA
DesignDesign strategy, e.g. RISC, CISC
TypeType of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
EncodingInstruction set encoding, e.g. Fixed or Variable
BranchingBranching evaluation, e.g. Condition register, Condition code, Compare and branch
EndiannessByte ordering, i.e. Little, Big, Bi
Page sizePrimary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
ExtensionsISA extensions, i.e. MMX, SSE, AltiVec, etc
OpenIs the architecture open or not? (as in free or proprietary)
PredecessorEarlier architecture(s) this one is based on, if it has a separate page
SuccessorLater architecture(s) based primarily on this one, if it has a separate page
Registers
Number and size of processor registers
General-purposeNumber of general-purpose registers (and size, if not indicated by bits=)
Floating pointNumber of floating-point registers (and size, if not indicated by bits=)
VectorNumber of vector registers (and size, if not indicated by bits=)

</syntaxhighlight> All fields are optional.

Example

SPARC
DesignerSun Microsystems
Bits64-bit (32 → 64)
Introduced1985
VersionV9 (1993)
DesignRISC
TypeRegister-Register
EncodingFixed
BranchingCondition code
EndiannessBi (Big → Bi)
Page size8 KiB
ExtensionsVIS 1.0, 2.0, 3.0
OpenYes
Registers
General-purpose31 (G0 = 0; non-global registers use register windows)
Floating point32

<syntaxhighlight lang="wikitext">

SPARC
DesignerSun Microsystems
Bits64-bit (32 → 64)
Introduced1985
VersionV9 (1993)
DesignRISC
TypeRegister-Register
EncodingFixed
BranchingCondition code
EndiannessBi (Big → Bi)
Page size8 KiB
ExtensionsVIS 1.0, 2.0, 3.0
OpenYes
Registers
General-purpose31 (G0 = 0; non-global registers use register windows)
Floating point32

</syntaxhighlight>

Parameters

All parameters are optional.

name
Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
designer
Designer of the architecture
bits
Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
introduced
Year introduced
version
Version/revision of architecture/ISA
design
Design strategy, e.g. RISC, CISC
type
Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
encoding
Instruction set encoding, e.g. Fixed or Variable
branching
Branching evaluation, e.g. Condition register, Condition code, Compare and branch
endianness
Byte ordering, e.g. Little, Big, Bi
page size
Primary size of page, e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
extensions
ISA extensions, e.g. MMX, SSE, AltiVec
open
Is the architecture open or not? (as in free or proprietary)
predecessor
Earlier architecture(s) this one is based on, if it has a separate page
successor
Later architecture(s) based primarily on this one, if it has a separate page
registers
Number and size of processor registers
gpr
Number of general-purpose registers (and size, if not indicated by bits=)
fpr
Number of floating-point registers (and size, if not indicated by bits=)
vpr
Number of vector registers (and size, if not indicated by bits=)

See also