Template:Infobox CPU architecture
File:Test Template Info-Icon - Version (2).svg Template documentation[view] [edit] [history] [purge]
.svg){kind=link}
| File:Lua-Logo.svg | This template uses Lua: |
This template is for CPU instruction set architectures.
Usage
<syntaxhighlight lang="wikitext"> </syntaxhighlight>
Description
<syntaxhighlight lang="wikitext">
| Designer | Designer of the architecture |
|---|---|
| Bits | Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit |
| Introduced | Year introduced |
| Version | Version/revision of architecture/ISA |
| Design | Design strategy, e.g. RISC, CISC |
| Type | Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory |
| Encoding | Instruction set encoding, e.g. Fixed or Variable |
| Branching | Branching evaluation, e.g. Condition register, Condition code, Compare and branch |
| Endianness | Byte ordering, i.e. Little, Big, Bi |
| Page size | Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions |
| Extensions | ISA extensions, i.e. MMX, SSE, AltiVec, etc |
| Open | Is the architecture open or not? (as in free or proprietary) |
| Predecessor | Earlier architecture(s) this one is based on, if it has a separate page |
| Successor | Later architecture(s) based primarily on this one, if it has a separate page |
| Registers | |
| Number and size of processor registers | |
| General-purpose | Number of general-purpose registers (and size, if not indicated by bits=) |
| Floating point | Number of floating-point registers (and size, if not indicated by bits=) |
| Vector | Number of vector registers (and size, if not indicated by bits=) |
</syntaxhighlight> All fields are optional.
Example
| Designer | Sun Microsystems |
|---|---|
| Bits | 64-bit (32 → 64) |
| Introduced | 1985 |
| Version | V9 (1993) |
| Design | RISC |
| Type | Register-Register |
| Encoding | Fixed |
| Branching | Condition code |
| Endianness | Bi (Big → Bi) |
| Page size | 8 KiB |
| Extensions | VIS 1.0, 2.0, 3.0 |
| Open | Yes |
| Registers | |
| General-purpose | 31 (G0 = 0; non-global registers use register windows) |
| Floating point | 32 |
<syntaxhighlight lang="wikitext">
| Designer | Sun Microsystems |
|---|---|
| Bits | 64-bit (32 → 64) |
| Introduced | 1985 |
| Version | V9 (1993) |
| Design | RISC |
| Type | Register-Register |
| Encoding | Fixed |
| Branching | Condition code |
| Endianness | Bi (Big → Bi) |
| Page size | 8 KiB |
| Extensions | VIS 1.0, 2.0, 3.0 |
| Open | Yes |
| Registers | |
| General-purpose | 31 (G0 = 0; non-global registers use register windows) |
| Floating point | 32 |
</syntaxhighlight>
Parameters
All parameters are optional.
- name
- Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
- designer
- Designer of the architecture
- bits
- Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
- introduced
- Year introduced
- version
- Version/revision of architecture/ISA
- design
- Design strategy, e.g. RISC, CISC
- type
- Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
- encoding
- Instruction set encoding, e.g. Fixed or Variable
- branching
- Branching evaluation, e.g. Condition register, Condition code, Compare and branch
- endianness
- Byte ordering, e.g. Little, Big, Bi
- page size
- Primary size of page, e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
- extensions
- ISA extensions, e.g. MMX, SSE, AltiVec
- open
- Is the architecture open or not? (as in free or proprietary)
- predecessor
- Earlier architecture(s) this one is based on, if it has a separate page
- successor
- Later architecture(s) based primarily on this one, if it has a separate page
- registers
- Number and size of processor registers
- gpr
- Number of general-purpose registers (and size, if not indicated by bits=)
- fpr
- Number of floating-point registers (and size, if not indicated by bits=)
- vpr
- Number of vector registers (and size, if not indicated by bits=)